This invention relates to resistor and capacitor structures and circuit elements and a method of fabricating the elements.
On-chip resistor and capacitor elements are used in many circuit applications. For example, capacitor elements can be used in internal and peripheral circuitry, and Electrostatic Discharge (ESD) networks. Peripheral circuits of semiconductor chips use capacitors for coupling and de-coupling of drivers, receivers, and power busses.
Decoupling capacitors are used on peripheral circuit power busses for noise stabilization, dampening and other applications. Standard decoupling capacitors are implemented into advanced semiconductor chips between the power rails for the standard power supply voltage xe2x80x9cVddxe2x80x9d and the substrate ground potential xe2x80x9cVss,xe2x80x9d in order to reduce noise when a chip is in operation. This capacitance is added using normal thin oxide devices with heavily doped silicon gate structures. Decoupling capacitor networks are provided with control circuitry to enable and disable capacitor structures. Decoupling capacitors have been applied with fuse elements, an electronic switch (B. Krauter et al., U.S. Pat. No. 5,506,457) and other circuit implementations.
Polysilcon-to-silicon capacitors are typically placed over a heavily doped implanted silicon region. Polysilicon-to-silicon capacitors are also designed over well structures. Capacitors can consist of a gate structure placed on a well or a substrate region. U.S. Pat. No. 4,914,546 (hereafter xe2x80x9cAlterxe2x80x9d) shows a heavily doped polysilicon gate structure over an n+ diffusion implant. Additionally, Alter shows that a heavily doped polysilicon film may be placed over a second heavily doped polysilicon film to construct a polysilicon-to-polysilicon capacitor.
U.S. Pat. No. 4,167,018 to Ohba et al. shows a heavily doped polysilicon-gate structure over a well, wherein the well is placed in a substrate. U.S. Pat. No. 4,914,497 to Kondo provides an MIS capacitor using an oxidation resist film as a dielectric material on a doped region. U.S. Pat. No. 5,244,825 to Coleman et al. Shows a heavily doped polysilicon gate structure over an n+ diffusion implant. Additionally, Coleman et al. show that a heavily doped polysilicon film can be placed over a second heavily doped polysilicon film to construct a polysilicon-to-polysilicon capacitor.
As gate oxide films scale to thinner dielectric films, the dielectric becomes less tolerant of over-voltage conditions. Oxide breakdown, measured by the charge-to-breakdown, decreases with dielectric scaling. Inter-dielectric film thicknesses are also decreasing, making circuitry more sensitive to voltage stressing, and electrical overstress (EOS) and electrostatic discharge (ESD) phenomena. This is a concern in metal oxide semiconductor field effect transistor (MOSFET) structures which must interface with voltages above the native voltage of the semiconductor process.
Overvoltage conditions are of particular concern in decoupling capacitors placed on the Input/Output (I/O) power rail.
The present invention is a circuit element, comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device.
According to another aspect of the invention, a capacitor element comprises a semiconductor substrate having a surface. A first dielectric film is formed on the surface of the substrate. A first polycrystalline silicon conductor is formed on the first dielectric film. A second dielectric film is formed on the first polycrystalline silicon conductor. A second polycrystalline silicon conductor is formed on the second dielectric film. One of the group consisting of the first and second polycrystalline silicon conductors has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device.